1. Field of the Invention
The present invention relates generally to the field of time division multiplexing, and specifically to the field of switching in computer networks.
2. Description of the Background Art
In the available art related to time division multiplexing and network switching, network operations are done synchronously to minimize errors. Digital switching equipment included in the networks needs to be synchronized to a single network clocking or synchronization source even if such synchronization is not required for the switching equipment""s internal operations. The common system clock source is normally phase-locked to a synchronization reference signal within the network using a commonly understood phase-locked loop.
The synchronization reference signals are usually originated by a Primary Reference Source (PRS) of the network, or derived therefrom. The synchronization reference signals often take the form of regular data carrying network signals. Since such signals usually carry the data streams grouped in blocks or frames, they have to contain information about the block or frame boundaries. It is the timing of the framing information that is used as the reference for network synchronization. The typical rate of such a reference signal is 8 kHz. The system clock is usually generated by a controlled frequency oscillator running at an average frequency, the frequency being a predetermined multiple of the reference signal rate. The frequency of the oscillator is controlled by a phase-locked loop, which is required to maintain a constant timing relationship between the phase of the system clock and a long-time average phase of the synchronization reference signal.
An available system clock oscillator is implemented by using a voltage controlled oscillator (VCO), which changes its frequency in response to changes in voltage. To facilitate measurement of the current timing (phase) relationship between the system clock and the synchronization reference signal, the system clock needs to be brought to the common form of all references. This is typically done by dividing the frequency of the system clock by a fixed-frequency divider.
The phase-locked loop uses a phase difference detector to measure the current timing (phase) relationship between the synchronization reference and the feedback signal derived from the system clock. From the measured phase difference, a specially chosen filter produces a signal controlling the system clock oscillator in a manner making the long-term average of the measured phase difference a constant value. The quantity of this average phase difference is typically irrelevant as long as it is constant. It is characteristic of the particular phase-locked loop design.
Available network synchronization phase-locked loops are often required to maintain only a very long-term (average) phase relationship between the reference and feedback signals. Short-term changes are ignored in order to minimize transfer of wander and jitter from the reference signal to the system clock. This is accomplished by designing, typically, a second order phase-locked loop with a transfer function bandwidth on the order of 0.1 Hz or less. An analog filter needed for such a loop would require using components having large values and size, which would make the system clock phase highly dependent on the system temperature. Therefore, such a phase-locked loop filter is typically implemented in the digital domain. Since such a filter operates at a relatively low frequency, it is feasible to implement its function as one of the procedures of an embedded real-time program executed by a microcontroller or similar integrated circuit. In particular, the same microcontroller that performs general Function Control may also be used for network synchronization.
The parameters of the filter can be controlled by the Function Control block in order to shorten the phase-lock acquisition time by temporarily widening the loop bandwidth. In a general case, the synchronization reference signals may differ among themselves in phase and/or frequency. Since the phase-locked loop is required to always bring the long-term average reference-to-feedback phase difference to a constant value, selecting a new reference, even one with an identical frequency, but a substantially different phase, results in a transition, forcing the system clock oscillator to an undesired frequency and causing a drift of the feedback signal with respect to the reference until their relative phase is brought back to the constant value.
From time to time, all of the external reference signals may be temporarily and simultaneously unsuitable for network synchronization purposes, but it may be desirable to continue running the system clock with the frequency and phase acquired before the simultaneous dysfunction occurred. In such case, the network synchronization card typically freezes the value controlling the system clock oscillator at the previously acquired level, allowing it to run free and assuming that its stability guarantees the continuation of the frequency and phase for time intervals that may be as long as 24 hours. This mode of operation of the network synchronization card is commonly referred to as a holdover mode.
In one available network synchronization card design, the mid-range frequency of such a voltage controlled oscillator is 19.44 MHz, i.e. it is 2430 times the typical 8 kHz reference frequency. The tuning range of the oscillator, relative to its center frequency, is typically on the order of +/xe2x88x9230 parts per million (PPM). The commonly required stability of the oscillator in the holdover mode is +/xe2x88x924.6 PPM.
The requirement of high stability in holdover mode(+/xe2x88x924.6 PPM) is difficult to satisfy by a controlled-frequency oscillator which, at the same time, is also required to be tuned over a relatively wide frequency range (+/xe2x88x9230 PPM). Oscillators that satisfy both requirements are expensive. There is therefore a need in the art for an efficient solution to this challenge.
To address the shortcomings of the available art, the present invention provides a method and a system (i) for eliminating a phase transient of a controlled-frequency oscillator caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and (ii) for running an controlled-frequency oscillator in a controlled long term holdover mode.
The present invention utilizes phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuitry including a relatively inexpensive oscillator that can be tuned over a relatively wide frequency range, wherein the requirement of high stability in holdover mode is satisfied by running the controlled-frequency oscillator in phase-lock with a signal derived from a stable, fixed-frequency (hence, relatively inexpensive) local oscillator, while any phase transient is eliminated and the previously acquired phase and frequency are preserved by precisely controlling the frequency division ratio of a tunable-frequency processing device.
A first advantage of the present invention therefore is the provision of a method for eliminating a phase transient of a controlled-frequency oscillator caused by replacing a first reference signal having a first reference phase and a first reference frequency by a second reference signal having a second reference phase and a second reference frequency when the first reference signal becomes corrupted or otherwise unavailable.
A second advantage is the provision of a method for eliminating a phase transient of a controlled-frequency oscillator utilizing a phase-locked loop (PLL), the method comprising the steps of (a) acquiring a first phase lock with a first reference signal having a first reference phase and a first reference frequency while using in the PLL a feedback signal having a feedback phase and a feedback frequency, the feedback signal being generated by a tunable frequency processing device operating with a constant, nominal frequency division ratio, the tunable frequency processing device being clocked by a clock signal generated by the controlled-frequency oscillator, the feedback frequency of the feedback signal being derived by dividing a frequency of the clock signal by the constant, nominal frequency division ratio of the tunable frequency processing device, the first phase lock resulting in a substantially constant first phase difference between the first reference phase and the feedback phase, and in a substantially constant first value of a control signal derived from the substantially constant first phase difference, (b) storing the first value of the control signal and using the first stored control value as a signal controlling the frequency of the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant frequency derived from the first stored value of the control signal, (c) selecting a second reference signal having a second frequency and a second phase, while continuing the control of the controlled-frequency oscillator with the first stored control value which results in the controlled-frequency oscillator running at the constant frequency derived from the first stored control value; (d) detecting a second phase difference between the second reference signal and the feedback signal; using the second phase difference to derive a signal for controlling the feedback frequency division ratio of the tunable frequency processing device, resulting in controlling the frequency and the phase of the feedback signal generated by the tunable frequency processing device in such a way that a second phase lock of the feedback signal with the second reference signal is acquired, wherein the frequency of the locked feedback signal is substantially equal to the frequency of the second reference signal, and the second phase difference is substantially equal to the first phase difference; and (e) setting the feedback frequency division ratio back to the nominal constant value; switching a frequency control of the controlled-frequency oscillator from the first stored control value to a signal derived from the second phase difference between the phase of the second reference signal and the phase of the feedback signal; and acquiring a third phase lock of the feedback signal to the second reference signal by controlling the frequency of the controlled-frequency oscillator, the third phase lock resulting in a substantially constant the second phase difference between the first reference phase and the feedback phase.
Still another advantage of the present invention is the provision of a method for running a controlled-frequency oscillator in a frequency-controlled holdover mode comprising the steps of (a) storing a pre-holdover mode value of the signal controlling the controlled-frequency oscillator, and applying the stored pre-holdover value to the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant pre-holdover mode frequency and a pre-holdover mode phase derived from the stored pre-holdover value of the control signal, (b) selecting a local reference signal, having a local reference frequency and a local reference phase, as a PLL reference in holdover mode; detecting a holdover phase difference between the local reference signal and a feedback signal generated by a tunable frequency processing device; the tunable feedback frequency processing device being clocked by the controlled-frequency oscillator, (c) using the holdover phase difference to derive a signal for controlling a variable frequency division ratio of the tunable feedback frequency processing device, resulting in controlling a frequency and a phase of the feedback signal in such a way that a first holdover phase lock of the feedback signal with the local reference signal is acquired, wherein the frequency and the phase of the locked feedback signal are substantially equal to the frequency and the phase of the local reference signal, (d) storing a holdover value of the signal controlling the tunable feedback frequency processing device, the holdover value of the controlling signal obtained as a result of the first holdover phase lock acquired in step (c), and applying the stored holdover value to the tunable feedback frequency processing device, resulting in the tunable feedback frequency processing device running with a constant, non-nominal frequency division ratio, (e) using the holdover phase difference to control frequency of the controlled-frequency oscillator in such a way that a second holdover phase lock of the feedback signal with the local reference signal is acquired, and (f) continuing in the second holdover phase lock state acquired in the step (e) for the required duration of the holdover mode, wherein the controlled-frequency oscillator continues to generate the system clock signal having the pre-holdover mode phase and the pre-holdover mode frequency.
Another advantage of the present invention is the provision of a method for switching a network synchronization card from a normal mode of operation to a holdover mode of operation using a phase-locked loop (PLL), the method comprising the steps of (a) storing a control value of a signal controlling an controlled-frequency oscillator at the level acquired as a result of phase lock during the normal mode of operation of the network synchronization card; applying the stored control value to the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant normal mode frequency and a constant normal mode phase derived from the stored normal value of the control signal, (b) selecting a local reference signal, having a local reference frequency and a local reference phase, as a PLL reference in holdover mode; detecting a holdover phase difference between the local reference signal and a feedback signal generated by a tunable frequency processing device; the tunable feedback frequency processing device being clocked by the controlled-frequency oscillator, (c) using the holdover phase difference to derive a signal for controlling a variable frequency division ratio of the tunable feedback frequency processing device, resulting in controlling a frequency and a phase of the feedback signal in such a way that a first holdover phase lock of the feedback signal with the local reference signal is acquired, wherein the frequency and the phase of the locked feedback signal are substantially equal to the frequency and the phase of the local reference signal, (d) storing a holdover value of the signal controlling the tunable feedback frequency processing device, the holdover value of the controlling signal obtained as a result of the first holdover phase lock acquired in step (c), and applying the stored holdover value to the tunable feedback frequency processing device, resulting in the tunable feedback frequency processing device running with a constant, non-nominal frequency division ratio, and (e) using the holdover phase difference to control frequency of the controlled-frequency oscillator in such a way that a second holdover phase lock of the feedback signal with the local reference signal is acquired.
Yet another advantage of the present invention is the provision of a system for eliminating a phase transient of a controlled-frequency oscillator utilizing a phase-locked loop (PLL) comprising (a) means for acquiring a first phase lock with a first reference signal having a first reference phase and a first reference frequency while using in the PLL a feedback signal having a feedback phase and a feedback frequency, the first phase lock resulting in a substantially constant first phase difference between the first reference phase and the feedback phase, and in a substantially constant first value of a control signal derived from the substantially constant first phase difference, (b) means for storing the first value of the control signal and using the stored first controlled value as a signal controlling the frequency of the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant frequency derived from the first stored value of the control signal, (c) a tunable frequency processing device operating with a controllable frequency division ratio, the tunable frequency processing device being clocked by a clock signal generated by the controlled-frequency oscillator, the tunable frequency processing device configured to generate the feedback signal, the feedback frequency of the feedback signal being derived by dividing a frequency of the clock signal by the controllable frequency division ratio of the tunable frequency processing device, (d) means for selecting a second reference signal having a second reference frequency and a second reference phase, while continuing the control of the controlled-frequency oscillator with the stored first control value which results in the controlled-frequency oscillator running at the constant frequency derived from the first stored control value, (e) means for detecting a second phase difference between the second reference signal and the feedback signal; using the second phase difference to derive a signal for controlling the controllable feedback frequency division ratio of the tunable frequency processing device, resulting in controlling the frequency and the phase of the feedback signal generated by the tunable frequency processing device in such a way that a second phase lock of the feedback signal with the second reference signal is acquired, wherein the frequency and the phase of the locked feedback signal are substantially equal to the frequency and the phase of the second reference signal, (f) means for setting the feedback frequency division ratio back to the nominal constant value, and (g) means for switching a frequency control of the controlled-frequency oscillator from the first stored control value to a signal derived from the second phase difference between the phase of the second reference signal and the phase of the feedback signal, the second phase difference being substantially equal to the first phase difference, wherein a third phase lock of the feedback signal to the second reference signal is acquired by controlling the frequency of the controlled-frequency oscillator.
Yet another advantage of the present invention is the provision of a method for switching a network synchronization card from a normal mode of operation to a holdover mode of operation using a phase-locked loop (PLL), the method comprising the steps of (a) storing a control value of a signal controlling an controlled-frequency oscillator at the level acquired as a result of phase lock during the normal mode of operation of the network synchronization card; applying the stored control value to the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant normal mode frequency and a constant normal mode phase derived from the stored normal value of the control signal, (b) selecting a local reference signal, having a local reference frequency and a local reference phase, as a PLL reference in holdover mode; detecting a holdover phase difference between the local reference signal and a feedback signal generated by a tunable frequency processing device; the tunable feedback frequency processing device being clocked by the controlled-frequency oscillator, (c) using the holdover phase difference to derive a signal for controlling a variable frequency division ratio of the tunable feedback frequency processing device, resulting in controlling a frequency and a phase of the feedback signal in such a way that a first holdover phase lock of the feedback signal with the local reference signal is acquired, wherein the frequency and the phase of the locked feedback signal are substantially equal to the frequency and the phase of the local reference signal, (d) storing a holdover value of the signal controlling the tunable feedback frequency processing device, the holdover value of the controlling signal obtained as a result of the first holdover phase lock acquired in step (c), and applying the stored holdover value to the tunable feedback frequency processing device, resulting in the tunable feedback frequency processing device running with a constant, non-nominal frequency division ratio, and (e) using the holdover phase difference to control frequency of the controlled-frequency oscillator in such a way that a second holdover phase lock of the feedback signal with the local reference signal is acquired.
Still another advantage of the present invention is the provision of a system for eliminating a phase transient of a controlled-frequency oscillator utilizing a phase-locked loop (PLL) comprising (a) means for acquiring a first phase lock with a first reference signal having a first reference phase and a first reference frequency while using in the PLL a feedback signal having a feedback phase and a feedback frequency, the first phase lock resulting in a substantially constant first phase difference between the first reference phase and the feedback phase, and in a substantially constant first value of a control signal derived from the substantially constant first phase difference, (b) means for storing the first value of the control signal and using the stored first controlled value as a signal controlling the frequency of the controlled-frequency oscillator, resulting in the controlled-frequency oscillator running at a constant frequency derived from the first stored value of the control signal, (c) a tunable frequency processing device operating with a controllable frequency division ratio, the tunable frequency processing device being clocked by a clock signal generated by the controlled-frequency oscillator, the tunable frequency processing device configured to generate the feedback signal, the feedback frequency of the feedback signal being derived by dividing a frequency of the clock signal by the controllable frequency division ratio of the tunable frequency processing device, (d) means for selecting a second reference signal having a second reference frequency and a second reference phase, while continuing the control of the controlled-frequency oscillator with the stored first control value which results in the controlled-frequency oscillator running at the constant frequency derived from the first stored control value, (e) means for detecting a second phase difference between the second reference signal and the feedback signal; using the second phase difference to derive a signal for controlling the controllable feedback frequency division ratio of the tunable frequency processing device, resulting in controlling the frequency and the phase of the feedback signal generated by the tunable frequency processing device in such a way that a second phase lock of the feedback signal with the second reference signal is acquired, wherein the frequency and the phase of the locked feedback signal are substantially equal to the frequency and the phase of the to second reference signal, (f) means for setting the feedback frequency division ratio back to the nominal constant value, and (g) means for switching a frequency control of the controlled-frequency oscillator from the first stored control value to a signal derived from the second phase difference between the phase of the second reference signal and the phase of the feedback signal, the second phase difference being substantially equal to the first phase difference, wherein a third phase lock of the feedback signal to the second reference signal is acquired by controlling the frequency of the controlled-frequency oscillator.